The present invention relates to a zero intermediate frequency receiver comprising a local frequency generating arrangement which is coupled to a pair of quadrature related mixers for mixing down a received signal to a pair of quadrature related signals to be demodulated in an in-phase signal path and in a quadrature signal path, a path comprising a cascade of at least a low pass filter and two amplifiers, and a DC-offset correction circuit between the amplifiers. Such a zero intermediate frequency receiver, which can be a direct conversion zero-IF receiver, a double conversion zero-IF receiver, or any other suitable zero-IF receiver, can be a digital paging receiver using a FSK (Frequency Shift Keying) or PSK (Phase Shift Keying) modulation scheme, but also a cordless or cellular receiver, or the like.
A receiver of the above kind is known from the published European Patent Application EP 0 594 894 A1. This European Patent Application discloses DC-offset correction in a zero intermediate frequency TDMA receiver or so-called zero-IF receiver. The received signal is mixed down by mixing with a local oscillator in a quadrature mixer. A DC-offset in the mixed down signal is compensated by baseband processing. For DC-offset correction a control loop is provided in both the in-phase signal path and the quadrature signal path. In addition to an overall correction loop in which DC-offset is corrected over many time slots, the receiver comprises an inner control loop for offset correction of a signal received within a time slot. This additional control loop may include a comparator comparing a difference signal in the overall control loop with zero and thereby acting as a one-bit analog-to-digital converter, cascaded with a successive approximation digital-to-analog converter determining in successive steps an offset correction value of the overall control loop so that the value of the difference signal is substantially zero. A zero intermediate frequency receiver can be a part of a message pager. Such pagers are narrow band receivers having a high gain in the in-phase and quadrature signal paths. With new paging protocols like APOC, FLEX and ERMES very long messages can be sent. During the reception of the signal the DC-drift has to be sufficiently small (typically&lt;3 .mu.V at the output of the mixer). Otherwise, zero crossings in the in-phase or I-signal and in the quadrature or Q-signal will be lost. Furthermore, when receiving relatively long messages, DC-offset correction can only be done during the reception of a sync-word (approximately once every second), without losing useful information, i.e. a part of a message to be received. For such receivers, the known DC-offset correction does not operate satisfactorily. Furthermore, pagers normally operate in a reception mode for receiving messages and in a sleep mode during which most of the reception circuitry is switched off. For saving the battery of the pager, the period in which the pager is in the reception mode should be as short as possible.